This patch extends the vf610 DDR memory controller code to support SW
leveling.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Agner <stefan.agner@toradex.com>

Series-to: u-boot
Series-cc: sbabic, Fabio Estevam <festevam@gmail.com>, Fabio Estevam <fabio.estevam@nxp.com>, mark.middleton@nxp.com, Marcel Ziswiler <marcel.ziswiler@toradex.com>, Stefan Agner <stefan@agner.ch>
Cover-letter-cc: sbabic, Fabio Estevam <festevam@gmail.com>, Fabio Estevam <fabio.estevam@nxp.com>, mark.middleton@nxp.com, Marcel Ziswiler <marcel.ziswiler@toradex.com>, Stefan Agner <stefan@agner.ch>
Series-version: 2

Series-changes: 2
 - Remove not needed #ifdef

Cover-letter:
ddr: vybrid: Support for vf610 built-in DDR3 memory calibration
This patch series provides code to perform read leveling - RDLVL, which
is adjusting the DQS strobe in relation to the DQ signals so that the
strobe edge is centered in the window of valid read data.

The code is based on Vybrid's Reference Manual's:
"VFxxx Controller Reference Manual, Rev. 0, 10/2016", page 1600,
10.1.6.16.4.1 "Software Read Leveling in MC Evaluation Mode"

and uses clarification provided by following NXP's community thread:
"Vybrid: About DDR leveling feature on DDRMC."
https://community.nxp.com/thread/395323

It depends on a BITMAP rework patch:
usb: composite: Move bitmap related operations to ./include/linux/bitmap.h
http://patchwork.ozlabs.org/patch/1006448/

END