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Commit e945816e authored by Jagan Teki's avatar Jagan Teki
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clk: sunxi: Add Allwinner H3/H5 CLK driver



Add initial clock driver for Allwinner H3/H5.

- Implement USB bus and USB clocks via ccu_clk_gate table for
  H3/H5, so it can accessed in common clk enable and disable
  functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table for
  H3/H5, so it can accessed in common reset deassert and assert
  functions from reset-sunxi.c

Signed-off-by: default avatarJagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard's avatarMaxime Ripard <maxime.ripard@bootlin.com>
parent 99ba4308
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