Skip to content
Commit aefc0b7a authored by Jagan Teki's avatar Jagan Teki
Browse files

clk: sunxi: h3: Implement EPHY CLK and RESET



EPHY CLK and RESET is available in Allwinner H3 EMAC
via mdio-mux node of internal PHY. Add the respective
clock and reset reg and bits.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: default avatarJagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger's avatarJoe Hershberger <joe.hershberger@ni.com>
parent 68620c96
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment