Skip to content
Commit 8c17cbdf authored by Jyri Sarha's avatar Jyri Sarha Committed by Tom Rini
Browse files

arm: am33xx: Initialize EMIF REG_PR_OLD_COUNT for BBB and am335x-evm



Initialize EMIF OCP_CONFIG registers REG_COS_COUNT_1, REG_COS_COUNT_2,
and REG_PR_OLD_COUNT field for Beaglebone-Black and am335x-evm. With
the default values LCDC suffers from DMA FIFO underflows and frame
synchronization lost errors. The initialization values are the highest
that work flawlessly when heavy memory load is generated by CPU. 32bpp
colors were used in the test. On BBB the video mode used 110MHz pixel
clock. The mode supported by the panel of am335x-evm uses 30MHz pixel
clock.

Signed-off-by: default avatarJyri Sarha <jsarha@ti.com>
Reviewed-by: default avatarTom Rini <trini@konsulko.com>
parent 177f14da
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment