Skip to content
Commit 337fcdc0 authored by Jagan Teki's avatar Jagan Teki
Browse files

clk: sunxi: Add Allwinner H6 CLK driver



Add initial clock driver for Allwinner H6.

- Implement UART bus clocks via ccu_clk_gate table for
  H6, so it can accessed in common clk enable and disable
  functions from clk_sunxi.c
- Implement UART bus resets via ccu_reset table for H6,
  so it can accessed in common reset deassert and assert
  functions from reset-sunxi.c

Signed-off-by: default avatarJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: default avatarAndre Przywara <andre.przywara@arm.com>
parent 8606f960
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment